1. Field of the Invention
The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a semiconductor device including a capacitor.
2. Discussion of Related Art
As semiconductor devices become more highly integrated, embodying high integration without reducing capacitance of capacitors becomes more important. Capacitance of a capacitor is in direct proportion to surface area but in inverse proportion to distance between capacitor electrodes. As semiconductor devices become more highly integrated, the distance between the capacitor electrodes become narrower. Thus, in order to keep capacitance of the capacitor constant, the surface areas thereof need to be increased. A cylinder type capacitor is an example of a capacitor having greater surface area.
FIGS. 1A through 1C are sequential views of a conventional method of forming a semiconductor device with a capacitor. In FIGS. 1A through 1C, the letter ‘a’ indicates a cell array region, and the letter ‘b’ indicates a peripheral circuit region.
Referring to FIG. 1A, a bottom dielectric layer 10 is formed on an entire surface of a semiconductor substrate 1. The bottom dielectric layer 10 is patterned to form bottom contact holes 9a and 9b. A bottom conductive layer (not shown) is formed to fill the contact holes 9a and 9b. The bottom conductive layer is planarized to form bottom contact plugs 12a and 12b at the cell array region a and the peripheral circuit region b, respectively. A first etch stopping layer 14, a supporting layer 16, a second etch stopping layer 18 and a sacrificial layer 19 are sequentially formed on a bottom dielectric layer 10 and the bottom contact plugs 12a and 12b. The layers 19, 18, 16 and 14 are patterned by a dry etch process, thereby forming an opening 13, exposing the bottom contact plug 12a and a part of the bottom dielectric layer 10 adjacent to the bottom contact plug 12a. 
Referring to FIG. 1B, a first conductive layer (not shown) is conformally formed on layers 10, 12a, 14, 16, 18, and 19. A part of the first conductive layer is removed to form a bottom electrode 20 covering the inside wall of the opening 1. The sacrificial layer 19 is removed by a wet etch process, thereby exposing an upper part of the outside wall of the bottom electrode 20. A dielectric layer 22 and a second conductive layer 24 are sequentially formed on layer 18 and a bottom electrode 20. The dielectric layer 22 and the second conductive layer 24 are patterned to form a dielectric pattern 22 and an upper electrode 24 that cover the bottom electrode 20 and the second etch stopping layer 18 at the cell array region a. Thus, a capacitor structure is completed. The second etch stopping layer 18 is exposed at the peripheral circuit region b.
Referring to FIG. 1C, a dielectric layer 26 is formed on layers 18 and 24, thereby covering the capacitor. At the peripheral circuit region b, the dielectric layer 26, the second etch stopping layer 18, the supporting layer 16 and the first etch stopping layer 14 are sequentially patterned by using a dry etch process, thereby forming an upper contact hole 29. The upper contact hole 29 is filled with a conductive layer (not shown) to form an upper contact plug 28 contacting with the bottom contact plug 12b. At the cell array region a, the dielectric layer 26 is patterned to form an upper electrode contact hole 31. The upper electrode contact hole 31 is filled with a conductive layer (not shown) to form an upper electrode contact plug 30 contacting with the upper electrode 24.
The ratio of etch rate of different materials is known as the selectivity of an etched process. In the conventional method, the sacrificial layer 19 and the supporting layer 16 are composed of oxide layers that have no wet etch selectivity ratio with respect to each other. Thus, in order to prevent the supporting layer 16 from being removed when the wet etch process is performed to form the bottom electrode 20, the second etch stopping layer 18 of silicon nitride is used. Thus, in conventional technology, the second etch stopping layer 18 is additionally deposited, and the layer 18 needs to be partially removed when an upper contact plug 28 is formed in a subsequent process. This adds to the complexity of the process, causes poor step coverage and bad profile of the upper contact hole 29 since the characteristics of layers (16, 18, and 26) are different from each other.
A need therefore exists for performing wet etch process without using a second etch stopping layer.